In context: TSMC has steadily raised the prices of its most advanced semiconductor process nodes over the past several years – so much so that one analysis suggests the cost per transistor hasn’t decreased in over a decade. Further price hikes, driven by tariffs and rising development costs, are reinforcing the notion that Moore’s Law is truly dead.
The Commercial Times reports that TSMC’s upcoming N2 2nm semiconductors will cost $30,000 per wafer, a roughly 66% increase over the company’s 3nm chips. Future nodes are expected to be even more expensive and likely reserved for the largest manufacturers.
TSMC has justified these price increases by citing the massive cost of building 2nm fabrication plants, which can reach up to $725 million. According to United Daily News, major players such as Apple, AMD, Qualcomm, Broadcom, and Nvidia are expected to place orders before the end of the year despite the higher prices, potentially bringing TSMC’s 2nm Arizona fab to full capacity.
Also see: How profitable are TSMC’s nodes: crunching the numbers
Unsurprisingly, Apple is getting first dibs. The A20 processor in next year’s iPhone 18 Pro is expected to be the first chip based on TSMC’s N2 process. Intel’s Nova Lake processors, targeting desktops and possibly high-end laptops, are also slated to use N2 and are expected to launch next year.
Earlier reports indicated that yield rates for TSMC’s 2nm process reached 60% last year and have since improved. New data suggests that 256Mb SRAM yield rates now exceed 90%. Trial production is likely already underway, with mass production scheduled to begin later this year.
With tape-outs for 2nm-based designs surpassing previous nodes at the same development stage, TSMC aims to produce tens of thousands of wafers by the end of 2025.
TSMC also plans to follow N2 with N2P and N2X in the second half of next year. N2P is expected to offer an 18% performance boost over N3E at the same power level and 36% greater energy efficiency at the same speed, along with significantly higher logic density. N2X, slated for mass production in 2027, will increase maximum clock frequencies by 10%.
As semiconductor geometries continue to shrink, power leakage becomes a major concern. TSMC’s 2nm nodes will address this issue with gate-all-around (GAA) transistor architectures, enabling more precise control of electrical currents.
Beyond 2nm lies the Angstrom era, where TSMC will implement backside power delivery to further enhance performance. Future process nodes like A16 (1.6nm) and A14 (1.4nm) could cost up to $45,000 per wafer.
Meanwhile, Intel is aiming to outpace TSMC’s roadmap. The company recently began risk production of its A18 node, which also features gate-all-around and backside power delivery. These chips are expected to debut later this year in Intel’s upcoming laptop CPUs, codenamed Panther Lake.
